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Platform Cable USB II
Table 6: JTAG/SPI/Slave Serial Port: 2-mm Connector Signals (Cont’d)
Pin
Number
JTAG
Configuration
MODE
SPI
Programming (1)
Slave-Serial
Configuration
Direction (2)
Description
JTAG Test Data In . This pin outputs the
10
TDI
–
–
Out
serial data stream transmitted to the TDI pin
on the first device in a JTAG chain.
JTAG Pseudo Ground. Use of this pin is
optional. PGND is pulled Low during JTAG
13
PGND
–
–
Out
operations; otherwise, it is high-Z. This pin is
connected to an open-drain driver and
requires a pull-up resistor on the target
system. (4)
JTAG Halt. Use of this pin is optional. Host
14
HALT
–
–
Out
applications can customize the behavior of
this signal. See HALT_INIT_WP Signal in
iMPACT, page 22 .
SPI Select . This pin is the active-Low SPI
4
–
SS
–
Out
chip select signal and should be connected
to the S (1) pin on the SPI flash device.
SPI Clock . This pin is the clock signal for
6
–
SCK
–
Out
SPI operations and should be connected to
the C (1) pin on the SPI flash PROM.
SPI Master-Input, Slave-Output . This pin
8
–
MISO
–
In
is the target serial output data stream and
should be connected to the Q (1) pin on the
SPI flash device.
SPI Master-Output Slave-Input . This pin
10
–
MOSI
–
Out
outputs the target serial input data stream
for SPI operations and should be connected
to the D (1) pin on the SPI flash device.
SPI Pseudo Ground . PGND is pulled Low
during SPI operations; otherwise, it is high-
Z. When connected to PROG_B on an
13
–
PGND
–
Out
FPGA, the FPGA will high-Z its SPI signals
while the cable is programming the SPI
flash. This pin is connected to an open-drain
driver and requires a pull-up resistor on the
target system. (4)
SPI Write Protect . This pin is reserved for
14
–
WP
–
–
future use. Do not connect for SPI
programming.
Slave Serial Configuration Reset . This pin
is used to force a reconfiguration of the
target FPGA(s) and should be connected to
4
–
–
PROG
Out
the PROG_B pin of the target FPGA for a
single-device system, or to the PROG_B pin
of all FPGAs in parallel in a daisy-chain
configuration.
Slave Serial Configuration Clock . FPGAs
load one configuration bit per CCLK cycle in
Slave Serial mode. CCLK should be
6
–
–
CCLK
Out
connected to the CCLK pin on the target
FPGA for single-device configuration, or to
the CCLK pin of all FPGAs in parallel in a
daisy-chain configuration.
DS593 (v1.2.1) March 17, 2011
www.xilinx.com
30
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